The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of\r\ncryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the\r\nrouting in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-rail\r\nsignals in WDDL design.We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain\r\nthey confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement\r\nand routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in treebased,\r\nsimple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh\r\narchitecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly\r\nbalanced routed signals in terms of wire length and switch number.
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